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ADuC7060
Table 105. SPICON MMR Bit Designations
Bit
15 to 14
13
12
11
10
9
8
7
6
5
4
3
Name
SPIMDE
SPITFLH
SPIRFLH
SPICONT
SPILP
SPIOEN
SPIROW
SPIZEN
SPITMDE
SPILF
SPIWOM
SPICPO
Description
SPI IRQ mode bits. These bits configure when the transmit/receive interrupts occur in a transfer.
[00] = transmit interrupt occurs when 1 byte has been transferred. Receive interrupt occurs when one or more bytes
have been received into the FIFO.
[01] = transmit interrupt occurs when 2 bytes have been transferred. Receive interrupt occurs when one or more
bytes have been received into the FIFO.
[10] = transmit interrupt occurs when 3 bytes have been transferred. Receive interrupt occurs when three or more
bytes have been received into the FIFO.
[11] = transmit interrupt occurs when 4 bytes have been transferred. Receive interrupt occurs when the receive FIFO
is full or 4 bytes are present.
SPI transmit FIFO flush enable bit.
Set this bit to flush the transmit FIFO. This bit does not clear itself and should be toggled if a single flush is required. If
this bit is left high, then either the last transmitted value or 0x00 is transmitted, depending on the SPIZEN bit. Any
writes to the transmit FIFO are ignored while this bit is set.
Clear this bit to disable transmit FIFO flushing.
SPI receive FIFO flush enable bit.
Set this bit to flush the receive FIFO. This bit does not clear itself and should be toggled if a single flush is required. If
this bit is set, all incoming data is ignored and no interrupts are generated. If set and SPITMDE = 0, a read of the
receive FIFO initiates a transfer.
Clear this bit to disable receive FIFO flushing.
Continuous transfer enable.
Set by user to enable continuous transfer. In master mode, the transfer continues until no valid data is available in the
transmit register. SS is asserted and remains asserted for the duration of each 8-bit serial transfer until the transmit
register is empty.
Cleared by user to disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid data exists
in the SPITX register, then a new transfer is initiated after a stall period of one serial clock cycle.
Loopback enable bit.
Set by user to connect MISO to MOSI and test software.
Cleared by user to be in normal mode.
Slave MISO output enable bit.
Set this bit for MISO to operate as normal.
Clear this bit to disable the output driver on the MISO pin. The MISO pin is open drain when this bit is cleared.
SPIRX overflow overwrite enable.
Set by user, the valid data in the receive register is overwritten by the new serial byte received.
Cleared by user, the new serial byte received is discarded.
SPI transmit zeros when transmit FIFO is empty.
Set this bit to transmit 0x00 when there is no valid data in the transmit FIFO.
Clear this bit to transmit the last transmitted value when there is no valid data in the transmit FIFO.
SPI transfer and interrupt mode.
Set by user to initiate transfer with a write to the SPITX register. Interrupt only occurs when Transmit is empty.
Cleared by user to initiate transfer with a read of the SPIr register. Interrupt occurs only when the receive is full.
LSB first transfer enable bit.
Set by user, the LSB is transmitted first.
Cleared by user, the MSB is transmitted first.
SPI wired or mode enable bit.
Set to 1 to enable the open-drain data output enable. External pull-ups are required on data out pins.
Clear for normal output levels.
Serial clock polarity mode bit.
Set by user, the serial clock idles high.
Cleared by user, the serial clock idles low.
Rev. 0 | Page 94 of 100
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